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S70GL-P MirrorBitTM Flash
S70GL02GP 2 Gigabit, 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
Data Sheet (Advance Information)
S70GL-P MirrorBitTM Flash Cover Sheet
Notice to Readers: This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
Publication Number S70GL-P_00
Revision 01
Issue Date December 4, 2006
Data
Sheet
(Advance
Information)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
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When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local sales office.
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S70GL-P MirrorBitTM Flash
S70GL-P_00_01 December 4, 2006
S70GL-P MirrorBitTM Flash Family
S70GL02GP 2 Gigabit, 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
Data Sheet (Advance Information)
General Description
The Spansion S70GL02GP 2 Gigabit MirrorbitTM Flash memory device is fabricated on 90 nm process technology. This device offers a fast page access time of 25 ns with a corresponding random access time of 120 ns. It features a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes the device an ideal product for today's embedded applications that require higher density, better performance and lower power consumption.
Distinctive Characteristics
Two 1024 Megabit (S29GL01GP) in a single 64-ball FortifiedBGA package (see publication S29GL-P_00 for full specifications) Single 3V read/program/erase (2.7-3.6 V) Enhanced VersatileI/OTM control
- All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC
Offered Packages
- 64-ball Fortified BGA
Suspend and Resume commands for Program and Erase operations Write operation status bits indicate program and erase operation completion Unlock Bypass Program command to reduce programming time Support for CFI (Common Flash Interface) Persistent and Password methods of Advanced Sector Protection WP#/ACC input
- Accelerates programming time (when VACC is applied) for greater throughput during system production - Protects first or last sector of each die, regardless of sector protection settings
90 nm MirrorBit process technology 8-word/16-byte page read buffer 32-word/64-byte write buffer reduces overall programming time for multiple-word updates Secured Silicon Sector region
- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number - Can be programmed and locked at the factory or by the customer
Uniform 64Kword/128KByte Sector Architecture
- S70GL02GP: two thousand forty-eight sectors
Hardware reset input (RESET#) resets device Ready/Busy# output (RY/BY#) detects program or erase cycle completion
100,000 erase cycles per sector typical 20-year data retention typical
Performance Characteristics
Max. Read Access Times (ns)* 2 Gb Parameter Random Access Time (tACC) Page Access Time (tPACC) CE# Access Time (tCE) OE# Access Time (tOE) V1 110 25 110 25 V2 120 25 120 25 V3 130 25 130 30 Program & Erase Times (typical values) Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VACC) Per Word Sector Erase Time (64 Kword Sector) 60 s 15 s 15 s 0.5 s Current Consumption (typical values) Random Access Read 8-Word Page Read Program/Erase Standby 30 mA 1 mA 50 mA 1 A
* Access times are dependent on VCC and VIO operating ranges. See Ordering Information page for further details. V1: VCC = 3.0-3.6 V. V2: VCC = VIO = 2.7-3.6 V. V3: VIO = 1.65-VCC, VCC = 3 V. ** Contact a sales representative for availability.
Publication Number S70GL-P_00
Revision 01
Issue Date December 4, 2006
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
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Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Recommended Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Special Handling Instructions for BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 LSE064--64 ball Fortified Ball Grid Array, 13 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Common Flash Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. 4. 5. 6. 7. 8.
List of Figures
Figure 2.1 Figure 2.2 64-ball Fortified Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 LSE064--64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm . . . . . . . . . . . . . . . . . . . . . . .6
List of Tables
Table 2.1 Table 3.1 Table 4.1 Table 5.1 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 S70GL02GP Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Autoselect Addresses in System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Erase And Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
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1.
Ordering Information
The ordering part number is formed by a valid combination of the following:
10 F A I 01 0 PACKING TYPE 0 = Tray (standard; see (Note 1) 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER (VIO range, protection when WP# =VIL) 01 = VIO = VCC = 2.7 to 3.6 V, highest address sector protected 02 = VIO = VCC = 2.7 to 3.6 V, lowest address sector protected V1 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, highest address sector protected V2 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, lowest address sector protected R1 = VIO = VCC = 3.0 to 3.6 V, highest address sector protected R2 = VIO = VCC = 3.0 to 3.6 V, lowest address sector protected TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE MATERIALS SET A = Pb (Note 3) F = Pb-free PACKAGE TYPE F = Fortified Ball Grid Array, 1.0 mm pitch package SPEED OPTION 11 = 110 ns 12 = 120 ns 13 = 130 ns DEVICE NUMBER/DESCRIPTION S70GL02GP 3.0 Volt-only, 2048 Megabit (256 M x 16-Bit/512 M x 8-Bit) Page-Mode Flash Memory Manufactured on 90 nm MirrorBitTM process technology
S70GL02GP
S70GL02GP Valid Combinations Base Part Number Speed (ns) 11 S70GL02GP 12 13 Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S70" and packing type designator from ordering part number. 3. Contact local sales representative for availability. FAI , FFI (Note 3) Package & Temperature Model Number R1, R2 01 (Note 3), 02 V1 (Note 3), V2 0, 2, 3 (Note 1) LSE064 (Fortified BGA) (Note 2) Pack Type Package Description
1.1
Recommended Combinations
Recommended Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific recommended combinations and to check on newly released combinations.
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2.
Input/Output Descriptions & Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions
Symbol A26-A0 DQ14-DQ0 DQ15 CE# OE# WE# VCC VIO VSS NC RY/BY# Type Input I/O I/O Input Input Input Supply Supply Supply No Connect Output Address lines for GL02GP Data input/output. DQ15: Data input/output in word mode . A-1: LSB address input in byte mode. Chip Enable. Output Enable. Write Enable. Device Power Supply. Versatile IO Input. Ground. Not connected internally. Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the device is actively erasing or programming. At High Z, the device is in ready. Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0DQ7 are active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active. Hardware Reset. Low = device resets and returns to reading array data. Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost sectors. At VHH, accelerates programming; automatically places device in unlock bypass mode. Should be at VIH for all other conditions. Reserved for future use. Description
BYTE# RESET# WP#/ACC RFU
Input Input Input Reserved
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2.1
Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning m ethods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Figure 2.1 64-ball Fortified Ball Grid Array
64-ball Fortified BGA Top View, Balls Facing Down
A8 RFU A7 A13 A6 A9 A5 WE# A4
B8 A22 B7 A12 B6 A8 B5 RESET# B4
C8 A23 C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 RFU
D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 RFU
E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 RFU
F8 A24 F7 BYTE# F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO
G8 A25 G7 DQ15/A-1 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 RFU
H8 RFU H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 RFU
RY/BY# WP#/ACC A3 A7 A2 A3 A1 RFU B3 A17 B2 A4 B1 A26
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2.2
LSE064--64 ball Fortified Ball Grid Array, 13 x 11 mm
Figure 2.2 LSE064--64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.50 LSE 064 N/A 13.00 mm x 11.00 mm PACKAGE MIN --0.40 0.79 NOM ------13.00 BSC. 11.00 BSC. 7.00 BSC. 7.00 BSC. 8 8 64 0.60 1.00 BSC. 1.00 BSC 0.50 BSC. --0.70 MAX 1.40 --0.91 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 6 7 NOTE 4. 5. 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3611 \ 16-038.15 \ 11.13.6
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3. Memory Map
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 3.1. Table 3.1 S70GL02GP Sector & Memory Address Map
Uniform Sector Size Sector Count Sector Range SA00 64 Kword/128 Kb 2048 : SA2047 Address Range (16-bit) 0000000h-000FFFFh : 7FF0000H-7FFFFFFh Sector Ending Address Notes Sector Starting Address
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA001-SA1022) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
4. Autoselect
Table 4.1 provides the device identification codes for the S70GL02GP. For more information on the autoselect function, refer to the S29GL-P data sheet (pulication number S29GL-P_00). Table 4.1 Autoselect Addresses in System
Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Secure Device Verify Sector Protect Verify Address (Base) + 00h (Base) + 01h (Base) + 0Eh (Base) + 0Fh (Base) + 03h (SA) + 02h xx01h/1h 227Eh/7Eh 2248h/48h 2201h/01h For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked. For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked. xx01h/01h = Locked, xx00h/00h = Unlocked Read Data (word/byte mode)
5. Erase And Programming Performance
Table 5.1 Erase And Programming Performance
Parameter Sector Erase Time Chip Erase Time Total Write Buffer Time (Note 3) Total Accelerated Write Buffer Programming Time (Note 3) Chip Program Time (Note 4) S70GL02GP S70GL02GP Typ (Note 1) 0.5 1024 480 432 1968 Max (Note 2) 3.5 4096 Unit sec sec s s sec Excludes system level overhead (Note 6) Comments Excludes 00h programming prior to erasure (Note 5)
Notes 1. Typical program and erase times assume the following conditions: 25C, 3.6 V VCC, 10,000 cycles, checkerboard pattern. 2. Under worst case conditions of -40C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 32-word write buffer operation. 4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
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6. BGA Package Capacitance
Parameter Symbol CIN COUT CIN2 RESET#, WP#/ACC CE#
Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Separated Control Pin Separated Control Pin
Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 VIN = 0
Typ 12 20 16 84 44
Max 20 24 20 90 50
Unit pF pF pF pF pF
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7.
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI infomation at the addresses given in Tables 7.2-7.4). All reads outside of the CFI address range, returns non-valid data. Reads from other sectors are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7.2-7.4. The system must write the reset command to return the device to reading array data. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: CFI Entry command */ *( (UINT16 *)base_addr + 0x55 ) = 0x0098; /* Example: CFI Exit command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* write CFI entry command */
/* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents. Table 7.1 CFI Query Identification String
Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (x8) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 7.2 System Interface String
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (x8) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0006h 0006h 0009h 0013h 0003h 0005h 0003h 0002h Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 mV VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 mV VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7.3 Device Geometry Definition
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch Addresses (x8) 4Eh 50h 52h 54h 56h 58h Data 001Bh 0002h 0000h 0006h 0000h 0001h Device Size = 2 byte 1Bh = 1 Gb Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 00FFh, 0003h, 0000h, 0002h =1 Gb 00FFh, 0001h, 0000h, 0002h = 512 Mb 00FFh, 0000h, 0000h, 0002h = 256 Mb 007Fh, 0000h, 0000h, 0002h = 128 Mb
N
Description
2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch
5Ah 5Ch 5Eh 60h 60h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h
00xxh 000xh 0000h 000xh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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Information)
Table 7.4 Primary Vendor-Specific Extended Query
Addresses (x16) 40h 41h 42h 43h 44h Addresses (x8) 80h 82h 84h 86h 88h Data 0050h 0052h 0049h 0031h 0033h Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0101b = 90 nm MirrorBit 46h 47h 48h 49h 4Ah 4Bh 4Ch 8Ch 8Eh 90h 92h 94h 96h 98h 0002h 0001h 0000h 0008h 0000h 0000h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 0008h = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV WP# Protection 4Fh 9Eh 00xxh 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported Description
45h
8Ah
0014h
4Dh
9Ah
00B5h
4Eh
9Ch
00C5h
50h
A0h
0001h
December 4, 2006 S70GL-P_00_01
S70GL-P MirrorBitTM Flash Family
11
Data
Sheet
(Advance
Information)
8.
Revision Summary
Section Description
Revision A0 (December 4, 2006) Initial Release.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
12
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006

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